A model for the automatic mapping of tasks to processors in heterogeneous multi-cluster architectures

Detalles Bibliográficos
Autor Principal: De Giusti, Laura Cristina
Otros autores o Colaboradores: Chichizola, Franco, Naiouf, Ricardo Marcelo, Ripoll, Ana, De Giusti, Armando Eduardo
Formato: Capítulo de libro
Lengua:inglés
Temas:
Acceso en línea:http://goo.gl/xRBRC8
Consultar en el Cátalogo
Resumen:This paper discusses automatic mapping methods for concurrent tasks to processors applying graph analysis for the relation among tasks, in which processing and communicating times are incorporated. Starting by an analysis in which processors are homogeneous and data transmission times do not depend on the processors that are communicating (a typical case in homogeneous clusters), we progress to extend the model to heterogeneous processors having the possibility of different communication levels, applicable to a multi- cluster. Some results obtained with the model and future work lines are presented, particularly, the possibility of obtaining the required optimal number of processors, keeping a constant efficiency level.
Notas:Formato de archivo: PDF. -- Este documento es producción intelectual de la Facultad de Informática - UNLP (Colección BIPA/Biblioteca)
Descripción Física:1 archivo (448 KB)

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245 1 0 |a A model for the automatic mapping of tasks to processors in heterogeneous multi-cluster architectures 
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520 |a This paper discusses automatic mapping methods for concurrent tasks to processors applying graph analysis for the relation among tasks, in which processing and communicating times are incorporated. Starting by an analysis in which processors are homogeneous and data transmission times do not depend on the processors that are communicating (a typical case in homogeneous clusters), we progress to extend the model to heterogeneous processors having the possibility of different communication levels, applicable to a multi- cluster. Some results obtained with the model and future work lines are presented, particularly, the possibility of obtaining the required optimal number of processors, keeping a constant efficiency level. 
534 |a Journal of Computer Science & Technology, 7(1), pp. 39-44 
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700 1 |a Naiouf, Ricardo Marcelo  |9 43376 
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